hy5ds283222bf(p) this document is a general product descript ion and is subject to change without notice. hynix semiconductor does not assume any responsibility for use of circuits described. no patent licenses are implied. rev. 1.0 / feb. 2005 1 128m(4mx32) gddr sdram hy5ds283222bf(p)
rev. 1.0 / feb. 2005 2 1 hy5ds283222bf(p) revision history no. history draft date remark 0.1 defined target spec. jun. 2004 0.2 1) changed idd & vdd_max 2) changed trcdwr, twr, cl, tck_max at 350mhz speed bin oct. 2004 1.0 changed idd spec. feb. 2005
rev. 1.0 / feb. 2005 3 1 hy5ds283222bf(p) description the hynix hy5ds283222 is a 134,217,728-bit cmos double dat a rate(ddr) synchronous dram, ideally suited for the point-to-point applications wh ich requires high bandwidth. the hynix 4mx32 ddr sdrams offer fully synchronous operatio ns referenced to both rising and falling edges of the clock. while all addresses and control inputs are latched on th e rising edges of the ck (fal ling edges of the /ck), data, data strobes and write data masks inputs are sampled on both rising and falling edges of it. the data paths are inter- nally pipelined and 2-bit prefetched to achieve very high bandwidth. all input and output voltage levels are compatible with sstl_2. features ? the hynix hy5ds283222bf(p) guarantee until 166mhz speed at dll_off condition ?1.8v v dd and v ddq wide range max power supply supports ? all inputs and outputs are compatible with sstl_2 interface ? 12mm x 12mm, 144ball fbga with 0.8mm pin pitch ? fully differential clock in puts (ck, /ck) operation ? double data rate interface ? source synchronous - data transaction aligned to bidirectional data strobe (dqs0 ~ dqs3) ? data outputs on dqs edges when read (edged dq) data inputs on dqs centers when write (centered dq) ? data(dq) and write masks(dm) latched on the both rising and falling edges of the data strobe ? all addresses and control inputs except data, data strobes and data masks latched on the rising edges of the clock ? write mask byte controls by dm (dm0 ~ dm3) ? programmable /cas latency 5 / 4 supported ? programmable burst length 2 / 4 / 8 with both sequential and interleave mode ? internal 4 bank operations with single pulsed /ras ? tras lock-out function supported ? auto refresh and self refresh supported ? 4096 refresh cycles / 32ms ? half strength and matched impedance driver option controlled by emrs ordering information note) hynix supports lead free parts for each speed grade with same specification, except lead free materials. we'll add "p" character after "f" for lead free product. for example, the part number of 300mhz lead free product is hy5ds283222bfp-33. part no. power supply clock frequency max data rate interface package hy5ds283222bf(p)-28 v dd /v ddq 1.8v 350mhz 700mbps/pin sstl_2 12mm x 12mm 144ball fbga hy5ds283222bf(p)-33 300mhz 600mbps/pin hy5ds283222bf(p)-36 275mhz 550mbps/pin hy5ds283222bf(p)-4 250mhz 500mbps/pin
rev. 1.0 / feb. 2005 4 1 hy5ds283222bf(p) pin configuration (top view) row and column address table items 4mx32 organization 1m x 32 x 4banks row address a0 ~ a11 column address a0 ~ a7 bank address ba0, ba1 auto precharge flag a8 refresh 4k ' 4 6 ' 4 6 ' 4 : ( ' 4 ' 0 ' 4 ' 4 ' 4 ' 4 ' 4 ' 4 ' 4 ' 4 ' 4 & |